Integrated circuit field effect transistors are widely used in microelectronic devices such as logic, memory and/or microprocessor devices. As is well known to those having skill in the art, an integrated circuit field effect transistor includes spaced apart source and drain regions in an integrated circuit substrate, such as a silicon semiconductor substrate, and an insulated gate on the integrated circuit substrate between the spaced apart source and drain regions. The insulated gate includes an insulating layer on the integrated circuit substrate and a gate electrode on the insulating layer opposite the integrated circuit substrate. The source and drain regions may be formed by implanting dopants into the substrate, thereby defining a channel region therebetween, beneath the gate electrode. Insulated gate field effect transistors also are referred to as MOS transistors or MOSFETs.
The gate electrode of an integrated circuit field effect transistor generally comprises doped polysilicon that may be doped, for example, with an n-type impurity, such as phosphorus or arsenic. Unfortunately, since polysilicon may have a rough surface morphology, it may be difficult to pattern a polysilicon layer to provide a polysilicon gate electrode.
Accordingly, it has been proposed to form a gate electrode using amorphous silicon that can have a smoother surface morphology than that of polysilicon. For example, as shown in FIG. 1, a gate insulating layer 53, such as silicon dioxide is formed on an integrated circuit substrate 51, such as a monocrystalline silicon substrate. An amorphous silicon layer 55 then is formed on the gate insulating layer 53 opposite the substrate 51. Also see U.S. Pat. No. 4,479,831 to Sandow et al. entitled Method of Making Low Resistance Polysilicon Gate Transistors and Low Resistance Interconnections Therefore Via Gas Deposited In-Situ Doped Amorphous Layer and Heat-Treatment and U.S. Pat. No. 5,563,093 to Koda et al. entitled Method of Manufacturing FET Semiconductor Devices With Polysilicon Gate Having Large Grain Sizes.
After forming and patterning the amorphous silicon layer 55, a thermal treatment generally is performed to convert the amorphous silicon gate 55 into polysilicon. Unfortunately, during the thermal treatment, stresses 57 may be formed in the polysilicon gate, which may lead to defects 59 in the gate insulating layer 53. These defects may cause the leakage current of the field effect transistor to unduly increase, and can lead to failure of the integrated circuit field effect transistor.
Attempts have been made to overcome the introduction of defects into the gate electrode. For example, see U.S. Pat. No. 5,614,428 to Kapoor entitled Process and Structure for Reduction of Channeling During Implantation of Source and Drain Region in Formation of MOS Integrated Circuit Structures, and U.S. Pat. No. 5,837,598 to Aronowitz et al. entitled Diffusion Barrier for Polysilicon Gate Electrode of MOS Device in Integrated Circuit Structure, and Method of Making Same.
Notwithstanding these and other attempts, it still is desirable to provide improved methods of forming gates for integrated circuit field effect transistors and integrated circuit field effect transistors so formed.